In integrated circuit design, during detail routing, design rule checking (DRC) is applied to check if there is any violation under different design rules. Design rules specify geometric and connectivity restrictions to enable manufacturing, accounting variability in semiconductor manufacturing processes. If there are violations, the system will try to fix them. The easiest way to do this is patching, by adding additional metal at the place where violation occurs.
In the prior art, the order of violations to be patched is predefined by heuristic method. These violations are sorted according to the design rules that they violate. The program tries to fix these violations one by one. However, some additional violations may be generated while patching one. As a result, this procedure repeats until all the violations have been fixed by patching.
FIG. 1 briefly shows how a prior art patching process works. First, the violation list is sorted. Then the process starts at the very beginning of the list, and patches through the whole list. Often, one or more violations are generated during the patching process, and they will be sorted based on the same order and processed at next iteration. The number of iterations to finish patching until there are no violations can vary. Note that after patching through all depths of violations, rip-up reroute will be applied. Thus, the effect of rip-up reroute will be taken into consideration.
Some violations cannot be resolved by simply patching or applying rip-up reroute. Therefore, these violations will remain in the design. By observation, the number of violations which remain after patching varies, and it is highly correlated to the order of rules to sort the violation list.